1. Technical Field
The invention relates generally to cache tag storage. More specifically, certain embodiments relates to techniques for caching sets of tags of a tag storage.
2. Background Art
Processors of all kinds have become more dependent on caches due to the relatively slow speed of memory in relation to the speed of a processor core. Numerous cache architectures have been utilized for decades. One common cache architecture is a set associative cache. Cache architectures have memory storage that stores data from system memory locations as well as a tag storage structure that stores sets of tags.
In standard cache hierarchy architecture, the closer to the processor core(s) a cache is located, generally, the smaller and faster the cache becomes. The smallest and fastest cache(s) generally reside on the processor core silicon die. On the other hand, the largest cache (LLC or last level cache) or caches sometimes reside off-die from the processor core(s). Accessing data that resides in an off-die cache as opposed to an on-die cache generally creates additional latency since it takes longer for the data to be transmitted to the processor core(s).
Each cache has a tag storage structure. If the processor needs data from a certain memory location, it can determine if the data is stored in a given cache by doing a comparison of the memory location address and the tag storage structure for the cache. If the tag storage structure is off-die, the latency to do a tag lookup will be greater than if the tag storage structure is on-die. Thus, although on-die tag storage structures increase the cost of the processor die because they take up valuable space, they help speed up execution by reducing the latencies of tag lookups versus off-die caches.